The present invention relates to a semiconductor memory device, and more particularly to a current amplification type mask-ROM having a bipolar junction transistor.
The structures of cells of mask-ROMs are generally divided into a NOR type and a NAND type. The mask-ROMs corresponding to a grade 4 Mb and a grade 16 Mb are employing the NAND type memory cell structure which is advantageous to high integration density.
FIG. 1 is an equivalent circuit view illustrating a part of the cell array of a general NAND type mask-ROM.
In the cell of the general NAND type mask-ROM, a plurality of string select transistors (M1 and M3: M2 and M4) which use the first and second string select lines S1 and S2 as their gate electrodes, are connected to a plurality of cell transistors M5, M7, . . . , M.sub.N-1 : M6, M, . . . , M.sub.N, thereby each forming the first and second string lines R1 and R2. Further, the first and second string lines R1 and R2 are connected in parallel to a bit line B/L in the cell of the general NAND mask-ROM, thereby forming a basic unit of a memory cell array. At this time, within one string line, a plurality of enhancement type cell transistors are connected to a plurality of depletion type cell transistors through an impurity diffusion layer. In FIG. 1, a reference numeral "D" indicates the depletion type transistor and the rest of transistors are the enhancement type transistors.
The operation of the mask-ROM is as follows.
First, during the stand-by operation, 0 volt is provided to the string select lines S1 and S2 and the common power supply voltage Vcc is provided to the word lines W/L1, W/L2, . . . , W/L.sub.N, thereby floating the bit line.
Second, during the read mode operation, 0 volt (or the power supply voltage Vcc) is provided to the first string select line S1 and the power supply voltage Vcc (or 0 volt) is provided to the second string select line S2, thereby selecting the first string line R1 (or the second string line R2). Thereafter, all of the unselected unit transistors of the unit cell transistors constituting the selected string line are turned on, and 0 volt is applied to the gate electrode of the selected transistor to thereby recognize whether the selected transistor is the enhancement type one or the depletion type one. This recognition results in reading data stored in the memory cell.
However, as the integration density is increased or as the number of unit cell transistors connected serially in the one string line is increased, the memory cell current of the NAND type mask-ROM becomes lower. Thereby, there are provided some problems in that it is difficult to read data and in that the data read speed becomes slow. As the operating voltage of the memory device becomes low, such a problem becomes more serious.
In order to improve the problems of the general NAND type mask-ROM, a new NAND mask-ROM is proposed, which has been referred to a Korean Patent Application No. 93-03299 (Tile of the Invention: A Semiconductor Memory Device, Inventors: Choi Jeong-Dal and Seo Kang-deok, Applicant: SAMSUNG Co., Ltd., Filing Date: 5 Mar. 1993) which corresponds to U.S. patent application Ser. No. 08/206,824, filed Mar. 7, 1994.
FIG. 2 shows a layout of the cell array of the prior art NAND type mask-ROM disclosed in the Korean Paten Application No. 93-03299.
In FIG. 2, a vertically long area taken along a long dot line is a mask pattern P1 for forming an N.sup.+ impurity diffusion layer. A horizontally long area taken along one dot and dash line is a mask pattern P2 for forming the string select line and the gate electrode of the cell transistor. A vertically long area taken along two dots and dash line is a mask pattern P3 for forming the bit line. A squared-shaped area taken along a short dot line is a mask pattern P4 for forming a depletion type channel. A squared-shaped area having oblique lines tilted to the right therein is a mask pattern P5 for forming a base of the bipolar junction transistor (hereinafter, referred to as "BJT"). Squared-shaped areas having oblique lines tilted to the left therein are mask patterns P6 and P7 for forming an emitter of the "BJT" and a P.sup.+ ion-implantation area. Squared-shaped areas having many dots therein are mask patterns P8 and P9 for forming contact windows. One contact window connects the emitter to the bit line and the other contact window connects the P.sup.+ ion-implantation area to a ground line. And, a mask pattern P10 taken along a solid line includes the mask pattern P9 and is used for forming the ground line.
FIG. 3 is the equivalent circuit view illustrating the NAND type mask-ROM of FIG. 2.
Referring to FIG. 3, there are repeatedly formed in the cell array part unit circuits having a BJT and two string lines R1 and R2 which are composed of the first and second string select transistors SM1 and SM2 and cell transistors M1, M2, M3, . . . , M.sub.N-1, M.sub.N, the BJT and the two string lines R1 and R2 being connected in parallel to each other. The emitters of the BJTs are connected to the bit lines B/L, the bases thereof to the drains of the first string select transistor SM1, and the collector thereof to the ground of the well (not shown) formed on the semiconductor substrate. The above first and second string select transistors SM1 and SM2 use the first and second string select lines S1 and S2 as their gate electrodes, and the above cell transistors M1, M2, M3, . . . , M.sub.N-1, M.sub.N use a plurality of word lines W/L1, W/L2, W/L3, . . . , W/L.sub.N-1, W/L.sub.N as their gate electrodes. Also, a plurality of ground lines for grounding the unit circuits are formed in the unit circuit one by one.
The equivalent circuit of FIG. 3 is the same as the mask-ROM of FIG. 1 except that the BJT is formed between the drain of the first string select transistor SM1 and the bit line B/L.
The BJT formed in between the drain of the first string select transistor SM1 and the bit line B/L increases the current flowing into the BJT from the bit line by .beta. when its current gain is .beta.. Thus, it is easy to read data generated due to reduction of the cell current and the time in reading the data becomes short.
FIGS. 4A and 4B are cross sectional views taken along the lines IV--IV and IV'--IV' of FIG. 2.
Referring to FIGS. 2, 3, 4A and 4B, the structure of the prior art NAND type mask-ROM will be explained hereinafter.
The prior art NAND type mask-ROM is composed of a P-type well 12; the string select lines S1 and S2 and the word lines W/L1, W/L2, W/L3, . . . , W/L.sub.N ; an N.sup.+ -type impurity diffusion layer 14; a depletion channel 16; an N.sup.- -type impurity diffusion layer 18; a p.sup.+ -type impurity diffusion layer 20; a p.sup.+ ion-implantation layer 22; contact windows 25 and 27; a bit line 26; and a ground line 28. The p-type well 12 is formed on a P-type (or N-type) semiconductor substrate 10. The string select lines S1 and S2 and the word lines W/L1, W/L2, W/L3, . . . , W/L.sub.N, are formed on the semiconductor substrate by using the mask pattern P2. The N.sup.+ -type impurity diffusion layer 14 is formed around the surface of the semiconductor substrate between the lines by the mask pattern P1 to thus become the source/drain region of each transistor. The depletion channel 16 is formed by impurity ion-implantation method using the mask pattern P4 to thus constitute the depletion type transistor D. The N.sup.- -type impurity diffusion layer 18 is formed by using the mask pattern P5 to each become the drain region of the first sting select transistor SM1 and the base of the BJT. The p.sup.+ -type impurity diffusion layer 20 is formed by using the mask pattern P6 to thus become the emitter of the BJT. The p.sup.+ ion-implantation layer 22 is formed by using the mask pattern P7. The contact window 25 is formed by using the mask pattern P8 and connects the p.sup.+ -type impurity diffusion layer 20 to the bit line. The contact window 27 is formed by using the mask pattern P9 and connects the p.sup.+ ion-implantation layer 22 to the ground line. The bit line 26 is formed by using the mask pattern P3 for contacting with the P.sup.+ impurity diffusion layer 20. And, the ground line 28 is formed by using the mask pattern P10 for contacting with the P.sup.+ ion-implantation layer 22.
With respect to FIG. 3, the BJT uses the p.sup.+ impurity diffusion layer 20 as its emitter E, the N.sup.- -type impurity diffusion layer 18 as its base B, and the p-type well 12 as its collector C. The well 12 is formed over the semiconductor substrate to thereby connect the collector to the ground line 28.
According to the Korean Patent Application No. 93-03299, the BJT is formed in between the drain region 20 of the string select transistor SM1 and the bit line 26. Here, the drain region 20 of the string select transistor SM1 becomes the base of the BJT and the bit line becomes the emitter thereof, so that it is possible to increase the cell current by .beta. times as large as the gain current of the BJT. Thus, it is easy to read data caused in the mask-ROM being on trend of the high integration density and the time in reading data becomes short.
However, in case that a plurality of "ON" cells are selected in the cell array to thereby activate the plurality of BJTs, a great deal of holes flow into the p-type well 12, so that the potential of the p-type well rises more than the built-in potential. Thereby, a P-N-P-N diode (which is composed of the P.sup.+ -type impurity diffusion layer 20--the N.sup.- -type impurity diffusion layer 18--the P-type well 12--the N.sup.+ -type impurity diffusion layer 14) is turned on and a great deal of current flow thus into the N.sup.+ -type impurity diffusion layer 14 which is connected to the ground line 28 in the P.sup.+ -type impurity diffusion layer 20 being the emitter of the BJT. This results in a malfunction and a latch-up in the cell. Further, owing to the rise of the potential of the P-type well, leakage current of the "OFF" cell causing the malfunction in the cell is increased and the bulk threshold voltage V.sub.TH is also reduced.
As the interval between the P.sup.+ -type impurity diffusion layer 20 and the P.sup.+ ion-implantation layer 22 for grounding the P-type well 12 becomes large, such a problem becomes more serious. Further, as the interval between the P.sup.+ -type impurity diffusion layer 20 and the P.sup.+ ion-implantation layer 22 becomes large, the parasite resist R.sub.WELL is increased in proportion to the size of the interval therebetween. As a result, the potential of the P-type well 12 rises because the holes flowing into the P-type well 12 are not effectively grounded.